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參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 9/88頁 |
| 文件大小： | 1156K |
| 代理商： | TMX320VC5421 |
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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions
NAME
TYPE
DESCRIPTION
DATA SIGNALS
PPA18 (MSB)
PPA17
PPA16
PPA15
PPA14
PPA13
PPA12
PPA11
PPA10
PPA9
PPA8
PPA7
PPA6
PPA5
PPA4§
PPA3
PPA2
PPA1
PPA0 (LSB)
I/O/Z
Parallel port address bus. The DSP can access the external memory locations by way of the external
memory interface using PPA[18:0] in external memory interface (EMIF) mode when the XIO pin is logic
high. PPA18 is a secondary output function of the SELA/B pin.
The PPA[17:0] pins are also multiplexed with the HPI interface. In HPI mode (XIO pin is low), the external
address pins PPA[17:0] are used by a host processor for access to the memory map by way of the
on-chip HPI. Refer to the Host-Port Interface (HPI) Signals section of this table for details on the
secondary functions of these pins.
These pins are placed into the high-impedance state when OFF is low.
PPD15 (MSB)
PPD14
PPD13
PPD12
PPD11
PPD10
PPD9
PPD8
PPD7
PPD6
PPD5
PPD4
PPD3
PPD2
PPD1
PPD0 (LSB)
I/O/Z
Parallel port data bus. The DSP uses this bidirectional data bus to access external memory when the
device is in external memory interface (EMIF) mode (the XIO pin is logic high).
This data bus is also multiplexed with the 16-bit HPI data bus. When in HPI mode, the bus is used to
transfer data between the host processor and internal DSP memory via the HPI. Refer to the HPI section
of this table for details on the secondary functions of these pins.
The data bus includes bus holders to reduce power dissipation caused by floating, unused pins. The bus
holders also eliminate the need for external pullup resistors on unused pins. When the data bus is not
being driven by the ’5421, the bus holders keep data pins at the last driven logic level. The data bus
keepers are disabled at reset and can be enabled/disabled via the BH bit of the BSCR register.
These pins are placed into high-impedance state when OFF is low.
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
A_INT0§
B_INT0§
A_INT1§
B_INT1§
A_NMI§
B_NMI§
I
External user interrupts. A_INT0–B_INT0 are prioritized and are maskable by the interrupt mask register
(IMR) and the interrupt mode bit. A_INT1 –B_INT1 can be polled and reset by way of the interrupt flag
register (IFR).
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the
IMR. When NMI is activated, the processor traps to the appropriate vector location.
A_RS§
B_RS§
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization
of the CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h
of program memory. RS affects various registers and status bits.
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
§These pins are Schmitt triggered inputs.
This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .
#This pin is used by Texas Instruments for device testing and should be left unconnected.
||This pin has an internal pulldown resistor.
A
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