參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 79/88頁
文件大?。?/td> 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
79
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HPI16 timing (continued)
timing requirements [H = 0.5t
c(CO)
] (see Figure 46 and Figure 53)
MIN
5
MAX
UNIT
ns
tsu(HBV-DSL)
th(DSL-HBV)
tsu(HBV-HSL)
th(HSL-HBV)
tsu(HAV-DSH)
tsu(HAV-DSL)
th(DSH-HAV)
tsu(HSL-DSL)
th(HSL-DSL)
tw(DSL)
tw(DSH)
Setup time, HAD valid before DS falling edge
Hold time, HAD valid after DS falling edge
Setup time, HAD valid before HAS falling edge
Hold time, HAD valid after HAS falling edge
5
ns
5
ns
5
ns
Setup time, address valid before DS rising edge (nonmultiplexed write)
Setup time, address valid before DS falling edge (nonmultiplexed mode)
Hold time, address valid after DS rising edge (nonmultiplexed mode)
Setup time, HAS low before DS falling edge
Hold time, HAS low after DS falling edge
Pulse duration, DS low
Pulse duration, DS high
5
ns
–4H – 5
ns
1
ns
5
ns
2
ns
30
ns
10
ns
Nonmultiplexed or multiplexed mode
Nonmulti lexed or multi lexed mode
(no increment) with no DMA activity.
Reads
12H
ns
Writes
14H
ns
Cycle time, DS rising edge to next DS
rising edge
Nonmultiplexed or multiplexed mode
Nonmulti lexed or multi lexed mode
(no increment) with 16-bit DMA activity.
Reads
18H
ns
Writes
20H
Nonmultiplexed or multiplexed mode
Nonmulti lexed or multi lexed mode
(no increment) with 32-bit DMA activity.
Reads
26H
ns
Writes
28H
tc(DSH-DSH)
Cycle time, DS rising edge to next DS
rising edge
Multiplexed (autoincrement) with no DMA
activity.
12H
ns
(In autoincrement mode, WRITE
au o c e e
timings are the same as READ
timings.)
Multiplexed (autoincrement) with 16-bit DMA
activity.
18H
ns
Multiplexed (autoincrement) with 32-bit DMA
activity.
26H
ns
Cycle time, DS rising edge to next DS rising edge writes to DSPINT and HINT
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
Setup time, SELA/B valid before DS falling edge
Hold time, SELA/B valid after DS rising edge
HAD stands for HCNTL0, HCNTL1, and HR/W.
DS refers to the logical OR of HCS and HDS.
8H
ns
tsu(HDV-DSH)
th(DSH-HDV)W
tsu(SELV-DSL)
th(DSH-SELV)
10
ns
0
ns
5
ns
0
ns
A
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