參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 29/88頁
文件大小： 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port (McBSP) (continued)
In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128 channel selection capability.
Twelve new registers (RCERCx–RCERHx and XCERCx–XCERHx) are used to enable the 128 channel
selection. The subadresses of the new registers are shown in Table 20. These new registers, functionally
equivalent to the RCERA0–RCERB1 and XCERA0–XCERB1 registers in the ’5420, are used to
enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the
128 channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112
to 127) of MCBSP1 for each DSP subsystem. See Figure 11, Table 8, Figure 12, and Table 9 for bit layout
and function of the receive and transmit registers .
15
14
13
12
11
10
9
8
RCERyz15
RCERyz14
RCERyz13
RCERyz12
RCERyz11
RCERyz10
RCERyz9
RCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
7
6
5
4
3
2
1
0
RCERyz7
RCERyz6
RCERyz5
RCERy4
RCERyz3
RCERyz2
RCERyz1
RCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
Note:
R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 11. Receive Channel Enable Registers Bit Layout for Partitions A to H
Table 8. Receive Channel Enable Registers for Partitions A to H
Bit
Name
Function
15–0
RCERyz(15:0)
Receive Channel Enable Register
RCERyz n = 0
Disables reception of nh channel in partition y.
RCERyz n = 1
Enables reception of nh channel in partition y.
Note:
y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0
A
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