參數(shù)資料
型號(hào): TMX320VC5421
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 18/88頁(yè)
文件大小: 1156K
代理商: TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
on-chip single-access RAM (SARAM)
The ’5421 subsystems A and B each have 32K 16-bit words of on-chip SARAM (4 blocks of 8K words). Each
of these SARAM blocks can be accessed once per machine cycle. This memory is intended to store data values
only. At reset, the SARAM is disabled. The SARAM can be enabled in data memory space by setting the DROM
bit in the PMST register.
on-chip shared RAM (DARAM)
The ’5421 has 128K 16-bit words of on-chip DARAM (16 blocks of 8K words) that is shared between the two
DSP subsystems. This memory is intended to store program only. Each subsystem is able to make one
instruction fetch from any location in shared memory each cycle. Neither subsystem CPU can write to the shared
memory as only the DMA can write to shared memory.
on-chip boot ROM
The ’5421 subsystems A and B each have 2K 16-bit words of on-chip ROM. This ROM is used for bootloading
functions only. Enabling the ROM maps out one 8K-word block of the shared program memory. The ROM can
be disabled by clearing bit 7 (ROMEN) of the general-purpose I/O (GPIO) register. Table 1 shows the
XIO/ROMEN modes. The ROM is enabled or disabled at reset for each subsystem depending on the state of
the GPIO0 pin for that subsystem.
Table 1. XIO/ROMEN Modes
XIO
ROMEN/GPIO0
MODE
0
x
Fetch internal from RAM
1
0
Fetch external
1
1
ROM enabled
extended program memory
The program memory space on the ’5421 device addresses up to 512K 16-bit words. The ’5421 device uses
a paged extended memory scheme in program space to allow access of up to 512K of program memory . This
extended program memory (each subsystem) is organized into eight pages (0–7), pages 0–3 are internal,
pages 4–7 are external, each 64K in length. (Pages 8–127 as defined by the program counter extension register
(XPC) are aliases for pages 4–7.) Access to the extended program memory is similar to the ’5420. To implement
the extended program memory scheme, the ’5421 device includes the following feature:
Two ’54x instructions are extended to use the additional two bits in the ’5421 device.
READA – Read program memory addressed by accumulator A and store in data memory
WRITA – Write data to program memory addressed by accumulator A
(Writes not allowed for CPUs to shared program memory)
program memory
The program memory is accessible on multiple pages, depending on the XPC value. Within these pages,
memory is accessible, depending on the address range.
Access in the lower 32K of each page is dependent on the state of OVLY.
OVLY = 0 – Program memory is accessed externally for all values of XPC.
OVLY = 1 – Program memory is accessed from local data/program DARAM for all values of XPC.
Access in the upper 32K of each page is dependent on the state of MP/MC and the value of XPC.
MP/MC = 0 – Program memory is accessed internally from shared DARAM for XPC = 0–3. Program
memory is accessed externally for XPC = 4–127.
MP/MC = 1 – Program memory is accessed externally for all values of XPC.
A
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