參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 43/88頁(yè)
文件大小： 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
McBSP control registers and subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within the
subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register. Table 20
shows the McBSP control registers and their corresponding subaddresses.
Table 20. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
NAME
ADDRESS
NAME
ADDRESS
NAME
ADDRESS
SUB-
ADDRESS
DESCRIPTION
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
MCR10
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
XCERG0
áááááááááááááááááá
DMA subbank addressed registers
SPCR10
39h
39h
39h
MCR11
XCERG1
SPCR11
49h
49h
49h
MCR12
XCERG2
SPCR12
SPCR22
35h
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
08h
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
ááááááááááááááá
01Ah
ááááááááááááááá
00h
Multichannel register 1
Transmit channel enable register partition G
Serial port control register 1
SPCR20
39h
SPCR21
49h
35h
01h
Serial port control register 2
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
SRGR10
39h
SRGR11
49h
SRGR22
MCR22
35h
RCERA2
35h
06h
Sample rate generator register 1
SRGR20
MCR20
39h
39h
SRGR21
MCR21
49h
49h
35h
35h
07h
09h
Sample rate generator register 2
Multichannel register 2
RCERA0
39h
RCERA1
49h
0Ah
Receive channel enable register partition A
35h
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
RCERD2
XCERD2
RCERD0
XCERD0
39h
39h
RCERD1
XCERD1
49h
49h
35h
XCERC2
011h
013h
Receive channel enable register partition D
Transmit channel enable register partition D
XCERC0
39h
XCERC1
49h
35h
35h
012h
Transmit channel enable register partition C
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
RCERH2
XCERH2
ááááááááááááááááááááááááááááááá
RCERH0
XCERH0
39h
39h
RCERH1
XCERH1
49h
49h
35h
35h
019h
01Bh
Receive channel enable register partition H
Transmit channel enable register partition H
35h
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register with
autoincrement (DMSDI) is used to access (read or write) the selected register.
A
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