參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 52/88頁(yè)
文件大?。?/td> 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VDD
= 3.3
±
0.3 V, IOH = MAX
IOL = MAX
MAX V
With internal pulldown
MIN
TYP
MAX
UNIT
VOH
VOL
IIZ
High-level output voltage
Low-level output voltage
2.4
V
0.4
V
Input current in high impedance
10
35
VDD
= MAX, VO = VSS to VDD
–10
–10
μ
A
TRST
Input current
(VI = VSS to VDD)
See pin descriptions
With internal pullups
–35
10
II
PPD[15:0]
Bus holders enabled, VDD = MAX,
VI = VSS to VDD
–175
175
μ
A
All other input-only pins
–10
10
IDDC
Supply current, both core CPUs
CVDD = 1.8 V, fx = 100 MHz§,
TC = 25
°
C
DVDD = 3.3 V, fclock = 100 MHz,
TC = 25
°
C#
90
mA
IDDP
Supply current, pins
54
mA
IDDA
Supply current, PLL
5
mA
IDDC
Supply current standby
Supply current, standby
IDLE2
PLL
×
n mode, 20 MHz input
PLL x n mode, 20 MHz input
2
mA
μ
A
pF
IDLE3
600
Ci
Co
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0, INT1, NMI, CLKIN, BCLKX, BCLKR, HAS, HCS, HDS1, HDS2, and HPIRS are
LVTTL-compatible.
§Clock mode: PLL
×
1 with external source
This value is based on 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with the program being executed.
#This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF = 0, full-duplex
operation of all six McBSPs at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation
is performed, refer to the Calculation of TMS320LC54x Power Dissipation Application Report(literature number SPRA164).
Input capacitance
10
Output capacitance
10
pF
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLoad
IOL
C
T
IOH
Output
Under
Test
50
Where:
IOL
IOH
VLoad = 1.5 V
CT
= 40 pF typical load circuit capacitance
= 1.5 mA (all outputs)
= 300
μ
A (all outputs)
Figure 21. 3.3-V Test Load Circuit
A
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