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參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 10/88頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | TMX320VC5421 |
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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME
DESCRIPTION
TYPE
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
XIO
I
The XIO pin is used to configure the parallel port as a host-port interface (HPI mode when XIO pin is low),
or as an asynchronous memory interface (EMIF mode when XIO pin is high).
At device reset, the XIO pin level determines the initialization value of the MP/MC bit (a bit in the
processor mode status (PMST) register). Refer to the memory section for details.
GENERAL-PURPOSE I/O PINS
A_XF
B_XF
O/Z
External flag output (latched software-programmable output-only signal). Bit-addressable. A_XF and
B_XF are placed into the high-impedance state when OFF is low.
A_GPIO0
B_GPIO0
I/O/Z
A_ROMEN
I
General-purpose I/O pins. The secondary function of these pins. In XIO mode,
the ROM enable (ROMEN) pins are used to enable the applicable on chip ROM
the ROM enable (ROMEN) pins are used to enable the applicable on-chip ROM
after reset.
B_ROMEN
A_GPIO1
B_GPIO1
I/O/Z
General-purpose I/O pins (software-programmable I/O signal). Values can be latched (output) by
writing into the GPIO register. The states of GPIO pins (inputs) can be read by reading the GPIO
register. The GPIO direction is also programmable by way of the DIRn field in the GPIO register.
A_GPIO2/BIO
B_GPIO2/BIO
I/O/Z
General-purpose I/O. These pins can be configured like GPIO0–GPIO1; however, as an input, the pins
operate as the traditional branch control bit (BIO). If application code does not perform BIO-conditional
instructions, these pins operate as general inputs.
PRIMARY
A_GPIO3 (A_TOUT)
I/O/Z
IOSTRB
O
When the device is in HPI mode and HMODE = 0 (multiplexed), these pins act
according to the general-purpose I/O control register. TOUT bit must be set to “1”
to drive the timer output on the pin IF TOUT
to drive the timer output on the pin. IF TOUT = 0, then these pins are
general-purpose I/Os. In EMIF mode (XIO = 1), these signals are active during
I/O space accesses.
MEMORY CONTROL SIGNALS
Program space select signal. The PS signal is asserted during external program space accesses. This
pin is placed into the high-impedance state when OFF is low.
0 then these pins are
B_GPIO3 (B_TOUT)
IS
PS§
This pin is also multiplexed with the HPI, and functions as the HDS1 data strobe input signal in HPI mode.
Refer to the HPI section of this table for details on the secondary function of this pin.
DS§
O/Z
Data space select signal. The DS signal is asserted during external data space accesses. This pin is
placed into the high-impedance state when OFF is low.
This pin is also multiplexed with the HPI, and functions as the HDS2 data strobe input signal in HPI mode.
Refer to the HPI section of this table for details on the secondary function of this pin.
IS
I/O space select signal. The IS signal is asserted during external I/O space accesses. This pin is placed
into the high-impedance state when OFF is low.
This pin is also multiplexed with the general-purpose I/O feature, and functions as the B_GPIO3
(B_TOUT) input/output signal in HPI mode. Refer to the General-Purpose I/O section of this table for
details on the secondary function of this pin.
MSTRB§
O/Z
Program and data memory strobe (active in EMIF mode). This pin is placed into the high-impedance
state when OFF is low.
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
§These pins are Schmitt triggered inputs.
This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .
#This pin is used by Texas Instruments for device testing and should be left unconnected.
||This pin has an internal pulldown resistor.
A
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