- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385002 > TMX320VC5421 (Texas Instruments, Inc.) DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 38/88頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | TMX320VC5421 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
general-purpose I/O (continued)
GPIO2 is a special case where the logic level determines the operation of BIO-conditional instructions on the
CPU. GPIO2 is always mapped as a general-purpose I/O, but the BIO function exists when this pin is configured
as an input.
hardware timer
The ’54x devices feature a 16-bit timing circuit with a 4-bit prescaler. The timer counter decrements by one at
every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer can
be stopped, restarted, reset, or disabled by specific status bits. The timer output pulse is driven on GPIO3 when
the TOUT bit is set to one in the general-purpose I/O control register. The device must be in HPI mode
(XIO = 0) to drive TOUT on the GPIO3 pin.
software-programmable phase-locked loop (PLL)
The clock generator provides clocks to the ’5421 device, and consists of a phase-locked loop (PLL) circuit. The
clock generator requires a reference clock input, which must be provided by using an external clock source. The
reference clock input is then divided by two (DIV mode) to generate clocks for the ’5421 device. Alternately, the
PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency
by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an
adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL is initially
started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is
locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock
circuitry allows the synthesis of new clock frequencies for use as master clock for the ’5421 device. Only
subsystem A controls the PLL. Subsystem B cannot access the PLL registers.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
PLL mode. The input clock (CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using
the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module.
Figure 19 shows the bit layout of the clock mode register and Table 14 describes the bit functions.
15
12
11
10
3
2
1
0
PLLMUL
PLLDIV
PLLCOUNT
PLLON/OFF
PLLNDIV
STATUS
R/W
R/W
R/W
R/W
R/W
R/W
When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate.
LEGEND:
R = Read, W = Write
Figure 19. Clock Mode Register (CLKMD)
A
相關PDF資料 |
PDF描述 |
|---|---|
| TMX320VC5509AGHH | TMS320VC5509A Fixed-Point Digital Signal Processor |
| TMX470R1A64PN | 16/32-Bit RISC Flash Microcontroller |
| TMXT504 | SAW BANDPASS FILTER |
| TN0104 | N-Channel Enhancement-Mode Vertical DMOS FET(擊穿電壓40V，低門限1.6V，N溝道增強型垂直DMOS結構場效應管) |
| TN0104 | N-Channel Enhancement-Mode Vertical DMOS FETs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320VC5441GGU | 制造商:Texas Instruments 功能描述: |
| TMX320VC5472GHK | 功能描述:IC DIGITAL SYSTEM PROCESSOR RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:- 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| TMX320VC549GGU100 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMX320VC549PGE-100 | 制造商:Texas Instruments 功能描述:320VC549PGE-100 |
| TMX320VC5501GZZ300 | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。