參數(shù)資料
型號： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 44/88頁
文件大?。?/td> 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMA subbank addressed registers (continued)
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 21 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.
Table 21. DMA Subbank Addressed Registers
NAME
ADDRESS
SUB-
DESCRIPTION
DMSRC0
56h/57h
ááááá
ááááá
56h/57h
DMA channel 0 source address register
DMDST0
56h/57h
DMA channel 0 destination address register
DMCTR0
ááááá
DMA channel 0 element count register
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
DMSRC1
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
DMCTR4
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 1 source address register
56h/57h
07h
DMA channel 1 element count register
DMMCR0
DMDST1
A
04h
05h
06h
DMA channel 0 transfer mode control register
DMA channel 1 transfer mode control register
ááááááááááááááááááááááááááááááááá
DMCTR1
DMA channel 1 destination address register
DMA channel 2 source address register
ááááááááááááááááááááááááááááááááá
56h/57h
56h/57h
0Fh
DMA channel 3 source address register
ááááááááááááááááááááááááááááááááá
DMCTR2
DMSFC2
DMSRC3
0Dh
56h/57h
DMA channel 2 sync select and frame count register
DMMCR2
0Eh
DMA channel 2 transfer mode control register
ááááááááááááááááááááááááááááááááá
áááááááá
ááááááááááááááááááááááá
56h/57h
16h
DMA channel 4 element count register
56h/57h
17h
DMA channel 4 sync select and frame count register
ááááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
DMMCR3
15h
56h/57h
18h
DMA channel 4 transfer mode control register
ááááááááááááááááááááááááááááááááá
DMSRC4
DMA channel 4 destination address register
DMDST4
DMSFC4
ááááááááááááááááááááááááááááááááá
DMMCR4
ááááááááááááááááááááááááááááááááá
DMA channel 5 sync select and frame count register
ááááááááááááááááááááááááááááááááá
56h/57h
1Dh
DMA channel 5 transfer mode control register
ááááááááááááááááááááááááááááááááá
56h/57h
56h/57h
1Eh
20h
DMA element index address register 0
ááááááááááááááááááááááááááááááááá
DMMCR5
DMA source program page address (common channel)
56h/57h
1Fh
DMA destination program page address (common channel)
ááááááááááááááááááááááááááááááááá
DMSRCP
DMIDX0
22h
DMA frame index register 0
DMDSTP
DMA frame index register 1
áááááááá
ááááááááááááááááááááááá
ááááááááááááááááááááááááááááááááá
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