參數(shù)資料
型號: TMX320VC5421
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號處理器
文件頁數(shù): 20/88頁
文件大小: 1156K
代理商: TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
bootloader (continued)
GPIO register bit 7 (ROMEN) is used to enable/disable the ROM after reset. The ROMEN bit reflects the status
of the ROMEN/GPIO0 pin for each core. ROMEN = 1 indicates that the ROM and the 8K-word program memory
block (00 E000h–00 FFFFh) are not available for the CPU. When ROMEN = 0, this 8K-word program memory
is available and the ROM are disabled.
A combination of interrupt flags and the bit values of an external memory location determine the selection of
the various boot options.
external interface (XIO)
The external interface (XIO) supports the ’5421 master boot modes and other external accesses. Its features
include:
Multiplexed with the HPI pins
Selection of XIO or HPI mode is determined by a dedicated pin (XIO)
Provides 512K words of external program space, 64K words of external data space, and 64K words of
external I/O space.
Different boot modes are selectable by the XIO, HMODE, and RS_A/B pins.
After reset, the control register bit ROMEN is always preset to 1.
While XIO = 0 during reset, host HPI mode is on, the host sees all RAM, and ROM is disabled. A host write to
002Fh releases the CPUs from reset; the 002Fh write by the host clears the ROMEN bit in the GPIO register.
While XIO = 1 and ROMEN = 1 during reset, the CPU starts from ROM (0FF80h) to do boot selection. After
branching to non-ROM area, the code changes the ROMEN bit to enable the RAM area occupied by ROM. While
XIO = 1 and ROMEN = 0 during reset, the CPU starts from external (0FF80h) to do boot selection.
Table 3 provides a complete description of HMODE, SELA/B, and XIO pin functionality.
Table 3. XIO/HPI Modes
HMODE
SELA/B
HPI MODES (XIO = 0)
XIO MODES (XIO = 1)
0
0
HPI muxed address/data subsystem A slave to host
SELA/B pin is multiplexed as PPA18 output.
0
1
HPI muxed address/data subsystem B slave to host
SELA/B pin is multiplexed as PPA18 output.
1
0
HPI non-muxed address/data subsystem A slave to host
SELA/B pin is multiplexed as PPA18 output.
1
1
HPI non-muxed address/data subsystem B slave to host
SELA/B pin is multiplexed as PPA18 output.
on-chip peripherals
All the ’54x devices have the same CPU structure; however, they have different on-chip peripherals connected
to their CPUs. The on-chip peripheral options provided are:
Software-programmable wait-state generator
Programmable bank-switching
Parallel I/O ports
Multichannel buffered serial ports (McBSPs)
A hardware timer
A software-programmable clock generator using a phase-locked loop (PLL)
A
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