參數(shù)資料
型號(hào): TMX320VC5421
廠商: Texas Instruments, Inc.
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 24/88頁(yè)
文件大?。?/td> 1156K
代理商: TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
16-bit bidirectional host-port interface (HPI16)
HPI16 memory map
The HPI16 is an enhanced 16-bit version of the ’C54x 8-bit host-port interface (HPI). The HPI16 is designed
to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface.
Figure 6 illustrates the available memory accessible by the HPI. Neither the CPU nor DMA I/O spaces can be
accessed using the host-port interface.
Page 0
McBSP
DXR/DRR
MMRegs Only
On-Chip
DARAM A
(32K Words)
Prog/Data
On-Chip
SARAM A
(32K Words)
Data Only
Hex
00 0000
00 001F
00 0020
00 005F
00 0060
00 7FFF
00 8000
00 FFFF
Page 1
On-Chip
Shared
DARAM 0
(32K Words)
Program Only
On-Chip
Shared
DARAM 1
(32K Words)
Program Only
Hex
01 0000
01 7FFF
01 8000
01 FFFF
Page 2
On-Chip
DARAM B
(32K Words)
Prog/Data
On-Chip
SARAM B
(32K Words)
Data Only
Hex
02 0000
02 7FFF
02 8000
02 FFFF
Page 3
On-Chip
Shared
DARAM 2
(32K Words)
Program Only
On-Chip
Shared
DARAM 3
(32K Words)
Program Only
Hex
03 0000
03 7FFF
03 8000
03 FFFF
02 005F
02 0060
McBSP
DXR/DRR
MMRegs Only
Subsystem A
Shared 0
Subsystem B
Subsystem B
Subsystem A
Shared 2
Shared 1
Shared 3
02 001F
02 0020
Reserved
Reserved
NOTES: A. All local memory is available to the HPI
B. The encoder maps CPU A Data Page 0 into the HPI Page 0. CPU B Data Page 0 is mapped into the HPI Page 2. Pages 1 and 3
are the on-chip shared program memory.
C. In pages 00 and 02, in the range of 0020–005F, only the following memory mapped registers are accessible: 20,21,30,31,40,41 (read
only), 22,23,32,33,42,43 (write only).
Figure 6. Memory Map Relative to Host-Port Interface HPI16
A
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