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參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 13/88頁 |
| 文件大小： | 1156K |
| 代理商： | TMX320VC5421 |
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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME
DESCRIPTION
TYPE
HOST-PORT INTERFACE (HPI) SIGNALS (CONTINUED)
PRIMARY
HD[15:0]
I/O/Z
PPD[15:0]
I/O/Z
Parallel bidirectional data bus. These pins are multiplexed with the external
interface pins and are used as an HPI interface when XIO = 0.
The data bus includes bus holders to reduce power dissipation caused by
floating, unused pins. The bus holders also eliminate the need for external pullup
resistors on unused pins. When the data bus is not being driven by the ’5421, the
bus holders keep address pins at the last driven logic level. The data bus keepers
are disabled at reset and can be enabled/disabled via the BH bit of the BSCR
register.
See the PPD signal descriptions. These pins are placed into the high-impedance
state when OFF is low.
HPI control inputs. Use PPA3 and PPA2 for the HCNTL0 and HCNTL1 values
during the HPI HPIC, HPIA, and HPID reads/writes. Only used in multiplexed
address/data mode (HMODE = 0).
These pins are shared with the external memory interface and are only used by
the HPI when the interface is in HPI mode (XIO pin is low). These pins are placed
into the high-impedance state when OFF is low.
HCNTL0
HCNTL1
I
PPA3
PPA2
O/Z
HAS§
I
PPA4§
O/Z
Address strobe input. Hosts with multiplexed address and data pins require HAS
to latch the address in the HPIA register. This signal is only used in HPI
multiplexed address/data mode (HMODE pin is low).
This pin is shared with the external memory interface and is only used by the HPI
when the interface is in HPI mode (XIO pin is low). This pin is placed into the
high-impedance state when OFF is low.
HCS§
I
MSTRB§
O/Z
HPI chip-select signal. This signal must be active during HPI transfers, and can
remain active between concurrent transfers.
This pin is shared with the external memory interface and is only used by the HPI
when the interface is in HPI mode (XIO pin is low). This pin is placed into the
high-impedance state when OFF is low.
HDS1§
HDS2§
I
PS§
DS§
O/Z
HPI data strobes. HDS1 and HDS2 are driven by the host read and write strobes
to control HPI transfers.
These pins are shared with the external memory interface and are only used by
the HPI when the interface is in HPI mode (XIO pin is low).
These pins are placed into the high-impedance state when OFF is low.
HR/W
I
R/W
O/Z
HPI read/write signal. This signal is used by the host to control the direction of an
HPI transfer.
This pin is shared with the external memory interface and is only used by the HPI
when the interface is in HPI mode (XIO pin is low).
This pin is placed into the high-impedance state when OFF is low.
HRDY
O/Z
READY
I
HPI data-ready output. The ready output informs the host when the HPI is ready
for the next transfer.
This pin is shared with the external memory interface and is only used by the HPI
when the interface is in HPI mode (XIO pin is low). HRDY is placed into the
high-impedance state when OFF is low.
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
§These pins are Schmitt triggered inputs.
This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .
#This pin is used by Texas Instruments for device testing and should be left unconnected.
||This pin has an internal pulldown resistor.
A
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