參數(shù)資料
型號(hào): TMX320VC5421
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 54/88頁(yè)
文件大?。?/td> 1156K
代理商: TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multiply-by-N clock option (PLL Enabled)
The frequency of the reference clock provided at the CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the
software-programmable phase-locked loop (PLL) section.
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 23)
PARAMETER
’5421-200
TYP
tc(CI)/N
UNIT
MIN
MAX
tc(CO)
td(CI-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
tp
N = Multiplication factor
Cycle time, CLKOUT
10
ns
Delay time, CLKIN high/low to CLKOUT high/low
4
10
16
ns
Fall time, CLKOUT
2
ns
Rise time, CLKOUT
2
ns
Pulse duration, CLKOUT low
H–2
H–1
H
ns
Pulse duration, CLKOUT high
H–2
H–1
H
ns
Transitory phase, PLL lock up time
30
s
timing requirements (see Figure 23)
’5421-200
MIN
20
20
20
UNIT
MAX
200
Integer PLL multiplier N (N = 1–15)
tc(CI)
Cycle time, CLKIN
PLL multiplier N = x.5
100
ns
PLL multiplier N = x.25, x.75
50
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
N = Multiplication factor
The multiplication factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range
(tc(CO))
Fall time, CLKIN
8
ns
Rise time, CLKIN
8
ns
Pulse duration, CLKIN low
5
ns
Pulse duration, CLKIN high
5
ns
tc(CO)
tc(CI)
tw(COH)
tf(CO)
tr(CO)
tf(CI)
CLKIN
CLKOUT
td(CI-CO)
tw(COL)
tr(CI)
tp
Unstable
tw(CIH)
tw(CIL)
Figure 23. External Multiply-by-One Clock Timing
A
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