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參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 33/88頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | TMX320VC5421 |
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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMA controller features
The ’5421 DMA has the following features:
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
Two DMA channels are available for external accesses: one for reads and one for writes.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers include configurable indexing modes. The
address can be held constant, postincremented, postdecremented, or adjusted by a programmable value.
For internal accesses, each read or write transfer can be initialized by selected events.
Supports 32-bit transfers for internal accesses only.
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external to external transfers.
A 16-bit DMA transfer requires four CPU clock cycles to complete — two cycles for reads and two cycles for
writes. This gives a maximum DMA throughput of 50 MBps. Since the DMA controller shares the DMA bus with
the HPI module, the DMA access rate is reduced when the HPI is active.
DMA accesses to external memory
The ’5421 DMAs supports external accesses to extended program, extended data, and extended I/O memory.
These overlay pages are only visible to the DMA controller. A maximum of two channels (one for reads, one
for writes) per DMA can be used for external memory accesses. The DMA external accesses require 9 cycles
(minimum) for external writes and 13 cycles (minimum) for external reads.
The control of the bus is arbitrated between the two CPUs and the two DMAs. While one DMA or CPU is in control
of the external bus, the other three components will be held off (via wait-states) until the current transfer is
complete. The DMA takes precedence over XIO requests. The HOLD/HOLDA feature of the ’5421 affects
external CPU transfers, as well as external DMA transfers. When an external processor asserts the HOLD pin
to gain control of the memory interface, the HOLDA signal is not asserted until all pending DMA transfers are
completed. To prevent a DMA from blocking out the CPUs or HOLD/HOLDA feature from accessing the external
bus, uninterrupted burst transfers are
not
supported by the DMAs. Subsequently, CPU and DMA arbitration
testing is performed for each external bus cycle, regardless of the bus activity. With the completion of each block,
the highest priority will be swapped.
For arbitration at the DSP subsystem level, the DMA requests (DMA_REQ_A or DMA_REQ_B) from either DMA
will be sent to both CPUs as shown in Figure 15. Regardless of which CPU controls the external pin interface
(XIO), both CPUs must send a grant (GRANT_A, GRANT_B) for control of the bus to be released to the DMAs.
Arbitration between CPUs is done using a request/grant scheme. Prior to accessing XIO of one of the CPUs,
software is responsible for asserting a request for access to the device pins and polling grant status until the
pins are granted to the requestor. If both CPUs request the bus simultaneously, subsystem A is granted priority.
For details on memory-mapped register bits pertaining to CPU XIO arbitration, see the general-purpose I/O
control register bits 6:4 (CORE SEL, XIO GRANT, XIO REQ) in Table 13.
At reset, the default is that subsystem A has access to the device pins. Accesses without a grant will be allowed,
but do not show up on the device pins.
A
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