參數(shù)資料
型號: TMX320VC5421
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號處理器
文件頁數(shù): 53/88頁
文件大?。?/td> 1156K
代理商: TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
divide-by-two, divide-by-four, and bypass clock option (PLL Disabled)
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in the software-programmable
phase-locked loop (PLL) section.
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 22,
and the recommended operating conditions table)
PARAMETER
’5421-200
UNIT
MIN
TYP
MAX
tc(CO)
tc(CO)
td(CIH-CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
This device utilizes a fully static design and therefore can operate with tc(CI) approaching
. The device is characterized at frequencies
approaching 0 Hz.
Cycle time, CLKOUT
40
2tc(CI)
2tc(CI)
ns
Cycle time, CLKOUT – bypass mode
40
ns
Delay time, CLKIN high to CLKOUT high/low
3
6
10
ns
Fall time, CLKOUT
2
ns
Rise time, CLKOUT
2
ns
Pulse duration, CLKOUT low
H–2
H–1
H
ns
Pulse duration, CLKOUT high
H–2
H–1
H
ns
timing requirements (see Figure 22)
’5421-200
UNIT
MIN
MAX
tc(CI)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
This device utilizes a fully static design and therefore can operate with tc(CI) approaching
. The device is characterized at frequencies
approaching 0 Hz.
Cycle time, CLKIN
20
ns
Fall time, CLKIN
8
ns
Rise time, CLKIN
8
ns
Pulse duration, CLKIN low
5
ns
Pulse duration, CLKIN high
5
ns
tr(CO)
tf(CO)
CLKOUT
CLKIN
tw(COL)
td(CIH-CO)
tf(CI)
tr(CI)
tc(CO)
tc(CI)
tw(COH)
tw(CIH)
tw(CIL)
Figure 22. External Divide-by-Two Clock Timing
A
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