參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 74/88頁(yè)
文件大小： 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
74
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
timing requirements for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b, CLKXP = 0
(see Figure 42)
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
tsu(BDRV-BCKXL)
th(BCKXL-BDRV)
tsu(BFXL-BCKXH)
tc(BCKX)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Setup time, BDR valid before BCLKX low
12
2 – 12H
ns
Hold time, BDR valid after BCLKX low
4
6 + 12H
ns
Setup time, BFSX low before BCLKX high
10
ns
Cycle time, BCLKX
12H
32H
ns
switching characteristics for McBSP as SPI master or slave: [H=0.5t
c(CO)
] CLKSTP = 10b,
CLKXP = 0
(see Figure 42)
PARAMETER
MASTER
SLAVE
UNIT
MIN
T – 5
MAX
T + 5
MIN
MAX
th(BCKXL-BFXL)
td(BFXL-BCKXH)
td(BCKXH-BDXV)
Hold time, BFSX low after BCLKX low§
Delay time, BFSX low to BCLKX high
ns
C – 5
C + 5
ns
Delay time, BCLKX high to BDX valid
–2
12
6H + 4
10H + 19
ns
tdis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from BCLKX
low
C – 2
C +10
ns
tdis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from BFSX
high
4H+ 4
8H + 17
ns
td(BFXL-BDXV)
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T =
BCLKX period = (1 + CLKGDV) * 2H
C =
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
§FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
Delay time, BFSX low to BDX valid
4H + 4
8H + 17
ns
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
BCLKX
BFSX
BDX
BDR
tsu(BDRV-BCKXL)
td(BCKXH-BDXV)
th(BCKXL-BDRV)
tdis(BFXH-BDXHZ)
tdis(BCKXL-BDXHZ)
th(BCKXL-BFXL)
td(BFXL-BDXV)
td(BFXL-BCKXH)
LSB
MSB
tsu(BFXL-BCKXH)
tc(BCKX)
Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
A
相關(guān)PDF資料
PDF描述
TMX320VC5509AGHH TMS320VC5509A Fixed-Point Digital Signal Processor
TMX470R1A64PN 16/32-Bit RISC Flash Microcontroller
TMXT504 SAW BANDPASS FILTER
TN0104 N-Channel Enhancement-Mode Vertical DMOS FET(擊穿電壓40V，低門限1.6V，N溝道增強(qiáng)型垂直DMOS結(jié)構(gòu)場(chǎng)效應(yīng)管)
TN0104 N-Channel Enhancement-Mode Vertical DMOS FETs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320VC5441GGU 制造商:Texas Instruments 功能描述:
TMX320VC5472GHK 功能描述:IC DIGITAL SYSTEM PROCESSOR RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:- 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
TMX320VC549GGU100 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TMX320VC549PGE-100 制造商:Texas Instruments 功能描述:320VC549PGE-100
TMX320VC5501GZZ300 制造商:Texas Instruments 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*