參數(shù)資料
型號： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 71/88頁
文件大?。?/td> 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
71
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial port timing (continued)
switching characteristics for the McBSP
[H=0.5t
c(CO)
] (see Figure 39 and Figure 40)
PARAMETER
MIN
MAX
UNIT
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
td(BCKRH-BFRV)
Cycle time, BCLKR/X
BCLKR/X int
4H
ns
Pulse duration, BCLKR/X high
BCLKR/X int
D–4
C–4
D+1
C+1
ns
Pulse duration, BCLKR/X low
BCLKR/X int
ns
Delay time, BCLKR high to internal BFSR valid
BCLKR int
–3
3
ns
td(BCKXH-BFXV)
Delay time BCLKX high to internal BFSX valid
Delay time, BCLKX high to internal BFSX valid
BCLKX int
–3
8
ns
BCLKX ext
2
15
tdis(BCKXH-BDXHZ)
Disable time BCLKX high to BDX high impedance following last data bit
Disable time, BCLKX high to BDX high impedance following last data bit
BCLKX int
–8
5
ns
BCLKX ext
1
19
Delay time, BCLKX high to BDX valid. This applies to all bits except the first
bit transmitted.
BCLKX int
0
11
lies to all bits exce t the first
BCLKX ext
5
20
td(BCKXH-BDXV)
DXENA = 0
BCLKX int
11
ns
Delay time, BCLKX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
BCLKX ext
20
DXENA = 1
BCLKX int
25
BCLKX ext
27
DXENA = 0
BCLKX int
–4
ten(BCKXH-BDX)
Enable time, BCLKX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
BCLKX ext
2
ns
DXENA = 1
BCLKX int
6
BCLKX ext
12
DXENA = 0
BFSX int
9
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid.§
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
BFSX ext
12
ns
DXENA = 1
BFSX int
25
BFSX ext
26
DXENA = 0
BFSX int
–1
ten(BFXH-BDX)
Enable time, BFSX high to BDX driven.§
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
BFSX ext
2
ns
DXENA = 1
BFSX int
BFSX ext
9
13
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of
that signal are
also inverted.
T=BCLKRX period = (1 + CLKGDV) * 2H
C=BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D=BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
§See the TMS320C54x Enhanced Peripherals Reference Set, Volume 5(literature number SPRU302) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
A
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