參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 42/88頁
文件大?。?/td> 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 19. Peripheral Memory-Mapped Registers for Each DSP Subsystem
NAME
ADDRESS
DEC
32
33
34
35
36
37
38
39
40
41
42
43
44
45–47
48
49
50
51
52
53
54–55
56
57
58–59
60
61
62
63
64
65
66
67
68–71
72
73
74–83
84
85
86
87
88
89–95
DESCRIPTION
HEX
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D–2F
30
31
32
33
34
35
36–37
38
39
3A–3B
3C
3D
3E
3F
40
41
42
43
44–47
48
49
4A–53
54
55
56
57
58
59–5F
DRR20
DRR10
DXR20
DXR10
TIM
PRD
TCR
—
SWWSR
BSCR
—
SWCR
HPIC
—
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
SPSA0
SPSD0
—
GPIO
—
CSIDR
—
DRR21
DRR11
DXR21
DXR11
—
SPSA1
SPSD1
—
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
See Table 20 for a detailed description of the McBSP control registers and their subaddresses.
See Table 21 for a detailed description of the DMA subbank addressed registers.
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
Timer Period Register
Timer Control Register
Reserved
Software Wait-State Register
Bank-Switching Control Register
Reserved
Software Wait-State Control Register
HPI Control Register (HMODE=0 only)
Reserved
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
McBSP 2 Subbank Address Register
McBSP 2 Subbank Data Register
Reserved
McBSP 0 Subbank Address Register
McBSP 0 Subbank Data Register
Reserved
General-Purpose I/O Register
Reserved
Chip Subsystem ID register
Reserved
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
McBSP 1 Subbank Address Register
McBSP 1 Subbank Data Register
Reserved
DMA Priority and Enable Control Register
DMA Subbank Address Register
DMA Subbank Data Register with Autoincrement
DMA Subbank Data Register
Clock Mode Register (CLKMD)
Reserved
A
memory-mapped registers (continued)
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