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| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 14/88頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | TMX320VC5421 |
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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
NAME
DESCRIPTION
TYPE
HOST-PORT INTERFACE (HPI) SIGNALS (CONTINUED)
PRIMARY
A_HINT
B_HINT
O/Z
PPA0
PPA1
O/Z
Host interrupt pin. HPI can interrupt the host by asserting this low. The host can
clear this interrupt by writing a “1” to the HINT bit of the HPIC register. Only
supported in HPI multiplexed address/data mode (HMODE pin is low). These pins
are placed into the high-impedance state when OFF is low.
HPIRS§
I
Host-port interface (HPI) reset pin. This signal resets the host port interface and both subsystems.
HMODE
I
Host mode select. When this pin is low, it selects the HPI multiplexed address/data mode. The
multiplexed address/data mode allows hosts with multiplexed address/data lines access to the HPI
registers HPIC, HPIA, and HPID. Host-to-DSP and DSP-to-host interrupts are supported in this mode.
When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts
with separate address/data buses to access the HPI address range by way of the 18-bit address bus
and the HPI data (HPID) register via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are
not supported in this mode.
SUPPLY PINS
AVDD
CVDD
DVDD
VSS
S
Dedicated power supply that powers the PLL. AVDD = 1.8 V. AVDD can be connected to CVDD.
Dedicated “clean” power supply that powers the core CPUs. CVDD = 1.8 V
Dedicated “dirty” power supply that powers the I/O pins. DVDD = 3.3 V
Digital ground. Dedicated ground plane for the device.
S
S
S
VSSA
S
Analog ground. Dedicated ground for the PLL. VSSA can be connected to VSS if digital and analog
grounds are not separated.
TEST PIN
TEST#
No connection
EMULATION/TEST PINS
TCK§
I
Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the
test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO)
occur on the falling edge of TCK.
TDI
I
Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK.
TDO
O/Z
Test data pin. The contents of the selected register is shifted out of TDO on the falling edge of TCK.
TDO is in high-impedance state except when the scanning of data is in progress. These pins are
placed into high-impedance state when OFF is low.
TMS
I
Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP
controller on the rising edge of TCK.
TRST||
I
Test reset. When high, TRST gives the scan system control of the operations of the device. If TRST is
driven low, the device operates in its functional mode and the IEEE 1149.1 signals are ignored. Pin with
internal pulldown device.
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal pullup resistor.
§These pins are Schmitt triggered inputs.
This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .
#This pin is used by Texas Instruments for device testing and should be left unconnected.
||This pin has an internal pulldown resistor.
A
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