- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385002 > TMX320VC5421 (Texas Instruments, Inc.) DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 39/88頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | TMX320VC5421 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
software-programmable phase-locked loop (PLL) (continued)
Table 14. Clock Mode Register (CLKMD) Bit Functions
BIT
NO.
BIT
NAME
PLLMUL
FUNCTION
15–12
PLL multiplier. PLLMUL defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV. See Table 15.
PLL divider. PLLDIV defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV. See Table 15.
11
PLLDIV = 0
Means that an integer multiply factor is used
PLLDIV
PLLDIV = 1
Means that a noninteger multiply factor is used
10–3
PLLCOUNT
PLL counter value. PLLCOUNT specifies the number of input clock cycles (in increments of16 cycles) for the
PLL lock timer to count before the PLL begins clocking the processor after the PLL is started. The PLL counter
is a down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the PLL
counter decrements by one.
The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked, so that only valid
clock signals are sent to the device.
2
PLLON/OFF
PLL on/off. PLLON/OFF enables or disables the PLL part of the clock generator in conjunction with the PLLNDIV
bit (see Table 16). Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when PLLON/OFF is high,
the PLL runs independently of the state of PLLNDIV.
1
PLLNDIV
PLLNDIV configures PLL mode when high or DIV mode when low. PLLNDIV defines the frequency multiplier in
conjunction with PLLDIV and PLLMUL. See Table 15.
Indicates the PLL mode.
0
STATUS
STATUS = 0
STATUS = 1
Indicates DIV mode
Indicates PLL mode
When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate.
Table 15. Multiplier Related to PLLNDIV, PLLDIV, and PLLMUL
PLLNDIV
PLLDIV
PLLMUL
MULTIPLIER
0
x
0–14
0.5
0
x
15
0.25
1
0
0–14
PLLMUL + 1
bypass (multiply by 1)§
1
0
15
1
1
0 or even
(PLLMUL + 1)/2
1
1
odd
PLLMUL/4
CLKOUT = CLKIN * Multiplier
§Indicates the default clock mode after reset
Table 16. VCO Truth Table
PLLON/OFF
PLLNDIV
VCO STATE
0
0
off
1
0
on
0
1
on
1
1
on
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMX320VC5509AGHH | TMS320VC5509A Fixed-Point Digital Signal Processor |
| TMX470R1A64PN | 16/32-Bit RISC Flash Microcontroller |
| TMXT504 | SAW BANDPASS FILTER |
| TN0104 | N-Channel Enhancement-Mode Vertical DMOS FET(擊穿電壓40V，低門限1.6V，N溝道增強型垂直DMOS結(jié)構(gòu)場效應管) |
| TN0104 | N-Channel Enhancement-Mode Vertical DMOS FETs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320VC5441GGU | 制造商:Texas Instruments 功能描述: |
| TMX320VC5472GHK | 功能描述:IC DIGITAL SYSTEM PROCESSOR RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:- 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| TMX320VC549GGU100 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMX320VC549PGE-100 | 制造商:Texas Instruments 功能描述:320VC549PGE-100 |
| TMX320VC5501GZZ300 | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。