參數(shù)資料
型號： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 36/88頁
文件大?。?/td> 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
subsystem communications
The ’5421 device provides two options for efficient core-to-core communications:
Core-to-core FIFO communications
DMA global memory transfer
FIFO data communications
The subsystems’ FIFO communications interface is shown in the ’5421 functional block diagram (Figure 1). Two
unidirectional 8-word-deep FIFOs are available in the device for efficient interprocessor communication: one
configured for core A-to-core B data transfers, and the other configured for core B-to-core A data transfers. Each
subsystem, by way of DMA control, can write to its respective output data FIFO and read from its respective
input data FIFO. The FIFOs are accessed using the DMAs I/O space, which is completely independent of the
CPU I/O space. The DMA transfers to or from the FIFOs can be synchronized to “receive FIFO not empty” and
“transmit FIFO not full” events, providing protection from overflow and underflow. Subsystems can interrupt
each other to flag when the FIFOs are either full or empty. The interprocessor interrupt request bit (IPIRQ) (bit
8 in the BSCR register (BSCR.8)) is set to 1 to generate a PINT in the other subsystem’s IFR.14. See the
interruptssection for more information.
DMA global memory transfers
The ’5421 enables each subsystem to transfer data directly between the memories that are CPU local via DMA
global memory transfers. The DMA global memory map is shown in Figure 13.
chip subsystem ID Register
The chip subsystem ID Register (CSIDR) is a read-only memory-mapped register located at 3Eh within each
DSP subsystem. This register contains three elements for electrically readable device identification. The ChipID
bits identify the type of 54x device (21h for 5421). The ChipRev bits contain the revision number of the device.
Lastly, the SubSysID contains a unique subsystem identifier.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Chip ID
Chip Rev
SubSysID
Figure 17. Chip subsystem ID Register
Table 12. Chip subsystem ID Register Bit Functions
BIT
NO.
BIT FIELD
NAME
FUNCTION
15 8
15–8
7–4
Chip ID
Chip Rev
54x device type Contains 21h for ’5421
54x device type. Contains 21h for ’5421.
Revision number of device (i.e., 0h for revision 0).
3 0
3–0
SubSysID
Identifier for DSP subsystem: A = 0h, B = 1h.
0h B
A
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