參數(shù)資料
型號(hào)： TMX320VC5421
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 48/88頁
文件大小： 1156K
代理商： TMX320VC5421
TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupts (continued)
Table 23. Bit Functions for IMR and IFR Registers for Each DSP Subsystem
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
15
Reserved
X
Register bit is reserved.
14
IPINT
0
IFR/IMR: Interprocessor IRQ has no interrupt pending/is disabled (masked).
1
IFR/IMR: Interprocessor IRQ has an interrupt pending/is enabled.
13
DMAC5
0
IFR/IMR: DMA Channel 5 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 5 has an interrupt pending/is enabled.
12
DMAC4
0
IFR/IMR: DMA Channel 4 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 4 has an interrupt pending/is enabled.
XINT1
0
IFR/IMR: McBSP_1 has no transmit interrupt pending/is disabled (masked).
11
1
IFR/IMR: McBSP_1 has a transmit interrupt pending/is enabled.
DMAC3
0
IFR/IMR: DMA Channel 3 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 3 has an interrupt pending/is enabled.
RINT1
0
IFR/IMR: McBSP_1 has no receive interrupt pending/is disabled (masked).
10
1
IFR/IMR: McBSP_1 has a receive interrupt pending/is enabled.
DMAC2
0
IFR/IMR: DMA Channel 2 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 2 has an interrupt pending/is enabled.
9
HPINT
0
IFR/IMR: Host-port interface has no DSPINT interrupt pending/is disabled (masked).
1
IFR/IMR: Host-port interface has an DSPINT interrupt pending/is enabled.
8
Reserved
X
Register bit is reserved.
XINT2
0
IFR/IMR: McBSP_2 has no transmit interrupt pending/is disabled (masked).
7
1
IFR/IMR: McBSP_2 has a transmit interrupt pending/is enabled.
DMAC1
0
IFR/IMR: DMA Channel 1 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 1 has an interrupt pending/is enabled.
RINT2
0
IFR/IMR: McBSP_2 has no receive interrupt pending/is disabled (masked).
6
1
IFR/IMR: McBSP_2 has a receive interrupt pending/is enabled.
DMAC0
0
IFR/IMR: DMA Channel 0 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 0 has an interrupt pending/is enabled.
5
XINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
4
RINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
3
TINT
0
IFR/IMR: Timer has no interrupt pending/is disabled (masked).
1
IFR/IMR: Timer has an interrupt pending/is enabled.
2
Reserved
X
Register bit is reserved.
1
INT1
0
IFR/IMR: Ext user interrupt pin 1 has no interrupt pending/is disabled (masked).
1
IFR/IMR: Ext user interrupt pin 1 has an interrupt pending/is enabled.
0
INT0
0
1
IFR/IMR: Ext user interrupt pin 0 has no interrupt pending/is disabled (masked).
IFR/IMR: Ext user interrupt pin 0 has an interrupt pending/is enabled.
A
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