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參數(shù)資料
| 型號： | TMX320VC5421 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 2/88頁 |
| 文件大?。?/td> | 1156K |
| 代理商： | TMX320VC5421 |
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TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description (continued)
The ’5421 also contains a host-port interface (HPI) that allows the ’5421 to be viewed as a memory-mapped
peripheral to a host processor. The ’5421 is pin-compatible with the TMS320VC5420.
Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program
instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can
be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that can all be performed in a single machine cycle. The ’5421 includes the
control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the ’5421 has
128K words of on-chip program memory that can be shared between the two subsystems.
The ’5421 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over
IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software
impacts, thus maximizing reuse of existing modem technologies and development efforts.
NOTE:
This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional
Overview (literature number SPRU307).
migration from the ’5420 to the ’5421
Customers who are migrating from the ’5420 to the ’5421 need to take into account the following differences
between the two devices.
The memory structure of the ’5421 has been changed to incorporate 128K x 16-bit words of shared memory.
The DMA of the ’5421 has been enhanced to provide access to external, as well as internal memory.
The HPI and DMA memory maps have been changed to incorporate the new memory ’5421.
2K x 16-bit words of ROM have been added to the ’5421 for bootloading purposes only.
The VCO pin on the ’5420 has been replaced with the HOLDA pin on the ’5421 and the HOLD pin was added
to the ’5421 at a previously unused pin location.
The McBSPs have been updated with a new mode that allows 128-channel selection capability.
McBSP CLKX/R pins can be used as inputs to internal clock rate generator for CLKS-like function without
the penalty of extra pins.
The SELA/B pin on ’5421 is changed to type I/O/Z for added functionality.
NOTE:
For more detailed information, see the 5420 to 5421 migration issues document .
A
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