參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 98/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 90 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Bit
Function
Type
Description
1
Primary MEMR
Command Alias
Enable
R/W
Controls PI7C7300D’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
2
Primary MEMW
Command Alias
Enable
R/W
Controls PI7C7300D’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
3
Secondary
MEMR
Command Alias
Enable
R/W
Controls PI7C7300D’s detection mechanism for matching memory
read retry cycles from the initiator on S1
0: exact matching for memory read retry cycles from initiator on the
S1 or S2 interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the S1 or S2 interface
Reset to 0
4
Secondary
MEMW
Command Alias
Enable
R/W
Controls PI7C7300D’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the S1 or S2 interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the S1 or S2 interface
Reset to 0
8:5
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
9
Enable Long
Request
R/W
Controls PI7C7300D’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
10
Enable
Secondary To
Hold Request
Longer
R/W
Control’s PI7C7300D’s ability to enable S1 or S2 to hold requests
longer.
0: internal S1 or S2 master will release REQ# after FRAME#
assertion
1: internal S1 or S2 master will hold REQ# until there is no
transactions pending in FIFO or until terminated by target
Reset to 0
11
Enable Primary
To Hold Request
Longer
R/W
Control’s PI7C7300D’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ# after FRAME#
assertion
1: internal Primary master will hold REQ# until there is no
transactions pending in FIFO or until terminated by target
Reset to 0
15:12
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
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