參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 13/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 13 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
3
SIGNAL DEFINITIONS
3.1
SIGNAL TYPES
Signal Type
Description
PI
PCI input (3.3V, 5V tolerant)
PIU
PCI input (3.3V, 5V tolerant) with weak pull-up
PID
PCI input (3.3V, 5V tolerant) with weak pull-down
PO
PCI output (3.3V)
PB
PCI tri-state bidirectional (3.3V, 5V tolerant)
PSTS
PCI sustained tri-state bi-directional (Active LOW signal which must be driven
inactive for one cycle before being tri-stated to ensure HIGH performance on a
shared signal line)
PTS
PCI tri-state output
POD
PCI output which either drives LOW (active state) or tri-state
3.2
PRIMARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
P_AD[31:0]
Y7, W7, Y8, W8,
V8, U8, Y9, W9,
W10, V10, Y11,
V11, U11, Y12,
W12, V12, V16,
W16, Y16, W17,
Y17, U18, W18,
Y18, U19, W19,
Y19, U20, V20,
Y20, T17, R17
PB
Primary Address/Data. Multiplexed address and data
bus. Address is indicated by P_FRAME# assertion.
Write data is stable and valid when P_IRDY# is
asserted and read data is stable and valid when
P_TRDY# is asserted. Data is transferred on rising
clock edges when both P_IRDY# and P_TRDY# are
asserted. During bus idle, PI7C7300D drives P_AD to
a valid logic level when P_GNT# is asserted.
P_CBE[3:0]
V9, U12, U16,
V19
PB
Primary Command/Byte Enables. Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C7300D drives
P_CBE[3:0] to a valid logic level when P_GNT# is
asserted.
P_PAR
U15
PB
Primary Parity. Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle
after the address phase (indicated by assertion of
P_FRAME#) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY# is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY# is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C7300D
drives P_PAR to a valid logic level when P_GNT# is
asserted.
P_FRAME#
W13
PSTS
Primary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of P_FRAME#
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted
state for one cycle.
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