參數(shù)資料
型號(hào)： PI7C7300DNAE
廠商： Pericom
文件頁(yè)數(shù)： 91/107頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 84 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Bit
Function
Type
Description
18
ISA enable
R/W
Modifies the bridge’s response to ISA I/O addresses, applying only to
those addresses falling within the I/O base and limit address registers
and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the last
768 bytes in each 1KB block
Reset to 0
19
VGA enable
R/W
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses from
primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
20
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
21
Master Abort
Mode
R/W
Control’s bridge’s behavior responding to master aborts on secondary
interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR# if enabled
Reset to 0
22
Secondary
Interface Reset
R/W
Controls the assertion of S1_RESET# or S2_RESET# signal pin on
the secondary interface
0: does not force the assertion of S1_RESET# or S2_RESET# pin
1: forces the assertion of S1_RESET# or S2_RESET#
Reset to 0
23
Fast Back-to-
Back Enable
R/W
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
24
Reserved
R/W
Reserved. Reset to 0
25
Reserved
R/W
Reserved. Reset to 0
26
Master Timeout
Status
R/WC
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
27
Discard Timer
P_SERR# enable
R/WC
This bit Is set to 1 and P_SERR# is asserted when either the primary
discard timer or the secondary S1 or S2 discard timer expire.
Reset to 0
31-28
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
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