參數(shù)資料
型號(hào)： PI7C7300DNAE
廠商： Pericom
文件頁(yè)數(shù)： 55/107頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 51 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Pass
Posted
Write
Delayed
Read
Request
Delayed
Write
Request
Delayed Read
Completion
Delayed Write
Completion
Delayed Write Request
No
4
No
Yes
Delayed
Read
Completion
No
3
Yes
No
Delayed
Write
Completion
Yes
No
Note: The superscript accompanying some of the table entries refers to any applicable
ordering rule listed in this section. Many entries are not governed by
these ordering rules; therefore, the implementation can choose whether or not the
transactions pass each other. The entries without superscripts reflect the PI7C7300D’s
implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is
followed by an explanation, and the ordering rules are referred to by number in Table
6-1. These ordering rules apply to posted write transactions, delayed write and read
requests, and delayed write and read completion transactions crossing PI7C7300D in the
same direction. Note that delayed completion transactions cross PI7C7300D in the
direction opposite that of the corresponding delayed requests.
1.
Posted write transactions must complete on the target bus in the order in which they
were received on the initiator bus. The subsequent posted write transaction can be
setting a flag that covers the data in the first posted write transaction; if the second
transaction were to complete before the first transaction, a device checking the flag
could subsequently consume stale data.
2.
A delayed read request traveling in the same direction as a previously queued posted
write transaction must push the posted write data ahead of it. The posted write
transaction must complete on the target bus before the delayed read request can be
attempted on the target bus. The read transaction can be to the same location as the
write data, so if the read transaction were to pass the write transaction, it would
return stale data.
3.
A delayed read completion must ‘‘pull’’ ahead of previously queued posted write
data traveling in the same direction. In this case, the read data is traveling in the
same direction as the write data, and the initiator of the read transaction is on the
same side of PI7C7300D as the target of the write transaction. The posted write
transaction must complete to the target before the read data is returned to the
initiator. The read transaction can be a reading to a status register of the initiator of
the posted write data and therefore should not complete until the write transaction is
complete.
4.
Delayed write requests cannot pass previously queued posted write data. For posted
memory write transactions, the delayed write transaction can set a flag that covers
the data in the posted write transaction. If the delayed write request were to complete
before the earlier posted write transaction, a device checking the flag could
subsequently consume stale data.
5.
Posted write transactions must be given opportunities to pass delayed read and write
requests and completions. Otherwise, deadlocks may occur when some bridges
which support delayed transactions and other bridges which do not support delayed
transactions are being used in the same system. A fairness algorithm is used to
arbitrate between the posted write queue and the delayed transaction queue.
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