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參數(shù)資料
| 型號： | PI7C7300DNAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 32/107頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 30 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Table 4-5 READ TRANSACTION PREFETCHING
Type of Transaction
Read Behavior
I/O Read
Prefetching never allowed
Configuration Read
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Memory Read
Upstream: Prefetching used or programmable
Memory Read Line
Prefetching always used
Memory Read Multiple
Prefetching always used
See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
4.7.4
DELAYED READ REQUESTS
PI7C7300D treats all read transactions as delayed read transactions, which means that the
read request from the initiator is posted into a delayed transaction queue. Read data from
the target is placed in the read data queue directed toward the initiator bus interface and
is transferred to the initiator when the initiator repeats the read transaction.
When PI7C7300D accepts a delayed read request, it first samples the read address, read
bus command, and address parity. When IRDY# is asserted, PI7C7300D then samples
the byte enable bits for the first data phase. This information is entered into the delayed
transaction queue. PI7C7300D terminates the transaction by signaling a target retry to the
initiator. Upon reception of the target retry, the initiator is required to continue to repeat
the same read transaction until at least one data transfer is completed, or until a target
response (target abort or master abort) other than a target retry is received.
4.7.5
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue,
PI7C7300D arbitrates for the target bus and initiates the read transaction only if all
previously queued posted write transactions have been delivered. PI7C7300D uses the
exact read address and read command captured from the initiator during the initial
delayed read request to initiate the read transaction. If the read transaction is a non-
prefetchable read, PI7C7300D drives the captured byte enable bits during the next cycle.
If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero
for all data phases. If PI7C7300D receives a target retry in response to the read
transaction on the target bus, it continues to repeat the read transaction until at least one
data transfer is completed, or until an error condition is encountered. If the transaction is
terminated via normal master termination or target disconnect after at least one data
transfer has been completed, PI7C7300D does not initiate any further attempts to read
more data.
If PI7C7300D is unable to obtain read data from the target after 2
24 (default) or 232
(maximum) attempts, PI7C7300D will report a system error. The number of attempts is
programmable. PI7C7300D also asserts P_SERR# if the primary SERR# enable bit is set
in the command register. See Section 7.4 for information on the assertion of P_SERR#.
Once PI7C7300D receives DEVSEL# and TRDY# from the target, it transfers the data read to the
opposite direction read data queue, pointing toward the opposite inter-face, before terminating the
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