參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 57/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 53 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the command register.
When PI7C7300D detects an address parity error on the secondary interface, the
following events occur:
If the parity error response bit is set in the bridge control register, PI7C7300D does
not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the
transaction to terminate in a master abort. If parity error response bit is not set,
PI7C7300D proceeds normally and accepts transaction if it is directed to or across
PI7C7300D.
PI7C7300D sets the detected parity error bit in the secondary status register.
PI7C7300D asserts P_SERR# and sets signaled system error bit in status register, if
both of the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the bridge control register.
7.2
DATA PARITY ERRORS
When forwarding transactions, PI7C7300D attempts to pass the data parity condition
from one interface to the other unchanged, whenever possible, to allow the master and
target devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C7300D.
7.2.1
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C7300D detects a data parity error during a Type 0 configuration write
transaction to PI7C7300D configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C7300D asserts
P_TRDY# and writes the data to the configuration register. PI7C7300D also asserts
P_PERR#. If the parity error response bit is not set, PI7C7300D does not assert
P_PERR#.
PI7C7300D sets the detected parity error bit in the status register, regardless of the
state of the parity error response bit.
7.2.2
READ TRANSACTIONS
When PI7C7300D detects a parity error during a read transaction, the target drives data
and data parity, and the initiator checks parity and conditionally asserts PERR#.
For downstream transactions, when PI7C7300D detects a read data parity error on the
secondary bus, the following events occur:
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