參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 103/107頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 95 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator
Target
Response
Master on Primary
Target on Primary
PI7C7300D does not respond. It detects
this situation by decoding the address as
well as monitoring the P_DEVSEL# for
other fast and medium devices on the
Primary Port.
Master on Primary
Target on Secondary
PI7C7300D asserts P_DEVSEL#,
terminates the cycle normally if it is able
to be posted, otherwise return with a retry.
It then passes the cycle to the appropriate
port. When the cycle is complete on the
target port, it will wait for the initiator to
repeat the same cycle and end with normal
termination.
Master on Primary
Target not on Primary nor
Secondary Port
PI7C7300D does not respond and the
cycle will terminate as master abort.
Master on Secondary
Target on the same
Secondary Port
PI7C7300D does not respond.
Master on Secondary
Target on Primary or the
other Secondary Port
PI7C7300D asserts S1_DEVSEL# or
S2_DEVSEL#, terminates the cycle
normally if it is able to be posted,
otherwise returns with a retry. It then
passes the cycle to the appropriate port.
When cycle is complete on the target port,
it will wait for the initiator to repeat the
same cycle and end with normal
termination.
Master on Secondary
Target not on Primary nor
the other Secondary Port
PI7C7300D does not respond.
15.2
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C7300D complies with the ordering
rules put forth in the PCI Local Bus Specification, Rev 2.2. The following table
summarizes the ordering relationship of all the transactions through the bridge.
PMW - Posted write (either memory write or memory write & invalidate)
DRR - Delayed read request (all memory read, I/O read & configuration read)
DWR - Delayed write request (I/O write & configuration write, memory write to
certain location)
DRC - Delayed read completion (all memory read, I/O read & configuration read)
DWC - Delayed write completion (I/O write & configuration write, memory write
to ccertain location
Cycle type shown on each row is the subsequent cycle after the previous shown on the
column.
Can Row Pass Column?
PMW
Column 1
DRR
Column 2
DWR
Column 3
DRC
Column 4
DWC
Column 5
PMW (Row 1)
No
Yes
DRR (Row 2)
No
Yes
DWR (Row 3)
No
Yes
DRC (Row 4)
No
Yes
No
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PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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PI7C8140AMAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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