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參數(shù)資料
| 型號(hào)： | PI7C7300DNAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 61/107頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 57 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Similarly, during upstream posted write transactions, when PI7C7300D responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
PI7C7300D asserts S_PERR# two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C7300D sets the parity error detected bit in the status register of the secondary
interface.
PI7C7300D captures and forwards the bad parity condition to the primary bus.
PI7C7300D completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR#, the following events occur:
PI7C7300D sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
PI7C7300D asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The posted write parity error bit of P_SERR# event disable register is not set.
-
The parity error response bit is set in the bridge control register of the secondary
interface.
-
The parity error response bit is set in the command register of the primary
interface.
-
PI7C7300D has not detected the parity error on the primary (initiator) bus which
the parity error is not forwarded from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR#, the following events occur:
PI7C7300D sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C7300D asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the bridge control register of the secondary
interface.
-
The parity error response bit is set in the command register of the primary
interface.
-
PI7C7300D has not detected the parity error on the secondary (initiator) bus
which the parity error is not forwarded from the secondary bus to the primary
bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR# will not be
asserted.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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