參數(shù)資料
型號(hào)： PI7C7300DNAE
廠商： Pericom
文件頁(yè)數(shù)： 70/107頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 65 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
When the locked delayed memory read request transaction moves to the head of the
delayed transaction queue, PI7C7300D initiates the transaction as a locked read
transaction by de-asserting LOCK# on the target bus during the first address phase, and
by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another
initiator), PI7C7300D waits to request access to the secondary bus until LOCK# is de-
asserted when the target bus is idle. Note that the existing lock on the target bus could
not have crossed PI7C7300D. Otherwise, the pending queued locked transaction would
not have been queued. When PI7C7300D is able to complete a data transfer with the
locked read transaction, the lock is established on the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the same
address, transaction type, and byte enable bits, PI7C7300D transfers the read data back to
the initiator, and the lock is then also established on the primary bus.
For PI7C7300D to recognize and respond to the initiator, the initiator’s subsequent
attempts of the read transaction must use the locked transaction sequence (de-assert
LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK#
sequence is not used in subsequent attempts, a master timeout condition may result.
When a master timeout condition occurs, SERR# is conditionally asserted (see Section
7.4), the read data and queued read transaction are discarded, and the LOCK# signal is
de-asserted on the target bus.
Once the intended target has been locked, any subsequent locked transactions initiated on
the initiator bus that are forwarded by PI7C7300D are driven as locked transactions on
the target bus.
The first transaction to establish LOCK# must be Memory Read. If the first transaction is
not Memory read, the following transactions behave accordingly:
- Type 0 Configuration Read/Write induces master abort
- Type 1 Configuration Read/Write induces master abort
- I/O Read induces master abort
- I/O Write induces master abort
- Memory Write induces master abort
When PI7C7300D receives a target abort or a master abort in response to the delayed
locked read transaction, this status is passed back to the initiator, and no locks are
established on either the target or the initiator bus. PI7C7300D resumes forwarding
unlocked transactions in both directions.
8.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C7300D ignores upstream lock and transactions. PI7C7300D will pass these
transactions as normal transactions without lock established.
8.3
ENDING EXCLUSIVE ACCESS
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