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參數(shù)資料
| 型號： | PI7C7300DNAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 14/107頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 14 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Name
Pin #
Type
Description
P_IRDY#
V13
PSTS
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the primary side. Once
asserted in a data phase, it is not de-asserted until the
end of the data phase. Before tri-stated, it is driven to a
de-asserted state for one cycle.
P_TRDY#
U13
PSTS
Primary TRDY (Active LOW). Driven by the target
of a transaction to indicate its ability to complete
current data phase on the primary side. Once asserted
in a data phase, it is not de-asserted until the end of the
data phase. Before tri-stated,
it is driven to a de-asserted state for one cycle.
P_DEVSEL#
Y14
PSTS
Primary Device Select (Active LOW). Asserted by
the target indicating that the device is accepting the
transaction. As a master, PI7C7300D waits for the
assertion of this signal within 5 cycles of P_FRAME#
assertion; otherwise, terminate with master abort.
Before tri-stated, it is driven to a
de-asserted state for one cycle.
P_STOP#
W14
PSTS
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to
stop the current transaction. Before tri-stated, it is
driven to a de-asserted state for one cycle.
P_LOCK#
V14
PSTS
Primary LOCK (Active LOW). Asserted by the
master for multiple transactions to complete.
P_IDSEL
Y10
PI
Primary ID Select. Used as a chip select line for Type
0 configuration accesses to PI7C7300D configuration
space.
P_PERR#
Y15
PSTS
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven
to a de-asserted state for one cycle.
P_SERR#
W15
POD
Primary System Error (Active LOW). Can be
driven LOW by any device to indicate a system error
condition. PI7C7300D drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S1_SERR# or S2_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
P_REQ#
W6
PTS
Primary Request (Active LOW). This is asserted by
PI7C7300D to indicate that it wants to start a
transaction on the primary bus. PI7C7300D de-asserts
this pin for at least 2 PCI clock cycles before asserting
it again.
P_GNT#
U7
PI
Primary Grant (Active LOW).
When asserted,
PI7C7300D can access the primary bus. During idle
and P_GNT# asserted, PI7C7300D will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
P_RESET#
Y5
PI
Primary RESET (Active LOW).
When P_RESET# is active, all PCI signals should be
asynchronously tri-stated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8140AMAE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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