參數(shù)資料
型號(hào): PI7C7300DNAE
廠商: Pericom
文件頁數(shù): 24/107頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝: 40
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 272-BBGA
供應(yīng)商設(shè)備封裝: 272-PBGA(27x27)
包裝: 管件
安裝類型: 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 23 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
4.4
DEVICE SELECT (DEVSEL#) GENERATION
PI7C7300D always performs positive address decoding (medium decode) when
accepting transactions on either the primary or secondary buses. PI7C7300D never does
subtractive decode.
4.5
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases.
A data phase is completed when IRDY# and either TRDY# or STOP# are asserted.
A transfer of data occurs only when both IRDY# and TRDY# are asserted during the
same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is
de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are
asserted. See Section 4.9 for further discussion of transaction termination.
Depending on the command type, PI7C7300D can support multiple data phase
PCI transactions. For detailed descriptions of how PI7C7300D imposes disconnect
boundaries, see Section 4.6.4 for write address boundaries and Section 4.7.3 read address
boundaries.
4.6
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions.
Table 4-2 shows the method of forwarding used for each type of write operation.
Table 4-2 WRITE TRANSACTION FORWARDING
Type of Transaction
Type of Forwarding
Memory Write
Posted (except VGA memory)
Memory Write and Invalidate
Posted
Memory Write to VGA memory
Delayed
I/O Write
Delayed
Type 1 Configuration Write
Delayed
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