參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 77/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 71 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Each secondary clock output is limited to no more than one load.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
12.1
PRIMARY INTERFACE RESET
PI7C7300D has a reset input, P_RESET#. When P_RESET# is asserted, the following
events occur:
PI7C7300D immediately 3-states all primary and secondary PCI interface signals.
PI7C7300D performs a chip reset.
Registers that have default values are reset.
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLK. PI7C7300D is not accessible during P_RESET#. After P_RESET# is de-
asserted, PI7C7300D remains inaccessible for 16 PCI clocks (Trhfa, page 128 of the PCI
Local Bus Specification Rev 2.2) before the first configuration transaction can be
accepted.
12.2
SECONDARY INTERFACE RESET
PI7C7300D is responsible for driving the secondary bus reset signals, S1_RESET# and
S2_RESET#. PI7C7300D asserts S1_RESET# or S2_RESET# when any of the
following conditions is met:
Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains
asserted as long as P_RESET# is asserted and does not de-assert until P_RESET# is
de-asserted.
The secondary reset bit in the bridge control register is set. Signal S1_RESET#
or S2_RESET# remains asserted until a configuration write operation clears the
secondary reset bit.
S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET# is
asserted, PI7C7300D immediately 3-states all the secondary PCI interface signals
associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in
asserting and de-asserting edges can be asynchronous to P_CLK.
When S1_RESET# or S2_RESET# is asserted, all secondary PCI interface control
signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD,
S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the
duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers
at the time of secondary reset are discarded.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140AMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge
PI7C8140AMAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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