參數(shù)資料
型號(hào)： PI7C7300DNAE
廠商： Pericom
文件頁(yè)數(shù)： 43/107頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 40 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Target Termination
Repsonse
Target Abort
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Note that when a target retry or target disconnect is returned and posted write data
associated with that transaction remains in the write buffers, PI7C7300D initiates another
write transaction to attempt to deliver the rest of the write data. If there is a target retry,
the exact same address will be driven as for the initial write trans-action attempt. If a
target disconnect is received, the address that is driven on a subsequent write transaction
attempt will be updated to reflect the address of the current DWORD. If the initial write
transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write
data to the target is performed before a target disconnect is received, PI7C7300D will use
the memory write command to deliver the rest of the write data. It is because an
incomplete cache line will be transferred in the subsequent write transaction attempt.
After the PI7C7300D makes 2
24 (default) write transaction attempts and fails to deliver
all posted write data associated with that transaction, PI7C7300D asserts P_SERR# if the
primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2)
and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2
of P_SERR# event disable register (offset 64h). PI7C7300D will report system error. See
Section 7.4 for a discussion of system error conditions.
4.9.3.3
DELAYED READ TARGET TERMINATION RESPONSE
When PI7C7300D initiates a delayed read transaction, the abnormal target responses can
be passed back to the initiator. Other target responses depend on how much data the
initiator requests. Table 4-9 shows the response to each type of target termination that
occurs during a delayed read transaction.
PI7C7300D repeats a delayed read transaction until one of the following conditions is
met:
PI7C7300D completes at least one data transfer.
PI7C7300D receives a master abort.
PI7C7300D receives a target abort.
PI7C7300D makes 2
24 (default) read attempts resulting in a response of target retry.
Table 4-9 RESPONSE TO DELAYED READ TARGET TERMINATION
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Target Retry
Re-initiate read transaction to target
Target Disconnect
If initiator requests more data than read from target, return target disconnect to
initiator.
Target Abort
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
After PI7C7300D makes 2
24(default) attempts of the same delayed read transaction on
the target bus, PI7C7300D asserts P_SERR# if the primary SERR# enable bit is set (bit 8
of command register for secondary bus S1 or S2) and the delayed-write-non-delivery bit
is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register
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