參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 67/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 62 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Table 7-6 ASSERTION OF S_PERR#
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
0 (asserted)
Read
Downstream
Secondary
x / 1
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / 1
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
0
2
Delayed Write
Upstream
Primary
1 / 1
0
Delayed Write
Upstream
Secondary
x / 1
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on
the initiator (primary) bus.
Table 7-7 shows assertion of P_SERR#. This signal is set under the following conditions:
PI7C7300D has detected P_PERR# asserted on an upstream posted write transaction
or S_PERR# asserted on a downstream posted write transaction.
PI7C7300D did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response
bit on the bridge control register must both be set.
The SERR# enable bit must be set in the command register.
Table 7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
P_SERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
0
2 (asserted)
Posted Write
Downstream
Secondary
1 / 1
0
3
Posted Write
Upstream
Primary
1 / 1
1
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
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