參數(shù)資料
型號: PI7C7300DNAE
廠商: Pericom
文件頁數(shù): 93/107頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝: 40
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 272-BBGA
供應(yīng)商設(shè)備封裝: 272-PBGA(27x27)
包裝: 管件
安裝類型: 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 86 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
14.1.28
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
Function
Type
Description
23:16
Arbiter Control
R/W
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [23:16] correspond to request inputs S1_REQ[7:0] or
S2_REQ[6:0]
0: low priority
1: high priority
Reset to 0
24
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
25
Priority of
Secondary
Interface
R/W
Controls whether the S1 or S2 interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
26
Arbiter Park
Function
R/W
Controls the arbiter’s park function.
0: park to last master
1: park to bridge port S1 or S2
Reset to 0
31:27
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.29
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
Bit
Function
Type
Description
16
Upstream (S1 or
S2 to P) Memory
Base and Limit
Enable
R/W
0: Upstream memory is the entire range except the down stream
memory channel
1: Upstream memory is confined to upstream Memory Base and Limit
(See offset 50
th and 54th for upstream memory range)
Reset to 0
17
Upstream (S1 or
S2 to P) Memory
Prefetchable
Enable
R/W
0: Upstream memory is prefetchable at Primary
1: Upstream memory is not prefetchable at Primary
Reset to 0
31:18
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
14.1.30
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch
Bit
Function
Type
Description
27:0
Hot Swap Time
Slot
R/W
Hot Swap time slot (15K PCI clocks)
Reset to 0003A98h
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