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參數(shù)資料
| 型號(hào)： | PI7C7300DNAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 25/107頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 24 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
4.6.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and
Invalidate” transactions.
When PI7C7300D determines that a memory write transaction is to be forwarded across
the bridge, PI7C7300D asserts DEVSEL# with medium timing and TRDY# in the next
cycle, provided that enough buffer space is available in the posted memory write queue
for the address and at least one DWORD of data. Under this condition, PI7C7300D
accepts write data without obtaining access to the target bus. The PI7C7300D can accept
one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted.
The write data is stored in an internal posted write buffers and is subsequently delivered
to the target. The PI7C7300D continues to accept write data until one of the following
events occurs:
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an
aligned 4KB boundary, depending on the transaction type.
The posted write data buffer fills up.
When one of the last two events occurs, the PI7C7300D returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C7300D
asserts its request on the target bus. This can occur while PI7C7300D is still receiving
data on the initiator bus. When the grant for the target bus is received and the target bus
is detected in the idle condition, PI7C7300D asserts FRAME# and drives the stored write
address out on the target bus. On the following cycle, PI7C7300D drives the first
DWORD of write data and continues to transfer write data until all write data
corresponding to that transaction is delivered, or until a target termination is received. As
long as write data exists in the queue, PI7C7300D can drive one DWORD of write data
each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing
through PI7C7300D and the initiator stalls, PI7C7300D will signal the last data phase for
the current transaction at the target bus if the queue empties. PI7C7300D will restart the
follow-on transactions if the queue has new data.
PI7C7300D ends the transaction on the target bus when one of the following conditions
is met:
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C7300D starts another
transaction to deliver the rest of the write data).
The target returns a target abort (PI7C7300D discards remaining write data).
The master latency timer expires, and PI7C7300D no longer has the target bus grant
(PI7C7300D starts another transaction to deliver remaining write data).
Section 4.9.3.2 provides detailed information about how PI7C7300D responds to target
termination during posted write transactions.
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