參數(shù)資料
型號(hào)： PI7C7300DNAE
廠商： Pericom
文件頁(yè)數(shù)： 28/107頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 27 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Delayed write transactions are posted as long as at least one open entry in the delayed
transaction queue exists. Therefore, several posted and delayed write transactions can
exist in data buffers at the same time. See Chapter 6 for information about how multiple
posted and delayed write transactions are ordered.
4.6.6
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C7300D can recognize and post fast back-to-back write transactions. When
PI7C7300D cannot accept the second transaction because of buffer space limitations, it
returns a target retry to the initiator. The fast back-to-back enable bit must be set in the
command register for upstream write transactions, and in the bridge control register for
downstream write transactions.
4.7
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C7300D. Delayed
read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows
the read behavior, prefetchable or non-prefetchable, for each type of read operation.
4.7.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C7300D performs
speculative DWORD reads, transferring data from the target before it is requested from
the initiator. This behavior allows a prefetchable read transaction to consist of multiple
data transfers. However, byte enable bits cannot be forwarded for all data phases as is
done for the single data phase of the non-prefetchable read transaction. For prefetchable
read transactions, PI7C7300D forces all byte enable bits to be turned on for all data
phases.
Prefetchable behavior is used for memory read line and memory read multiple
transactions, as well as for memory read transactions that fall into prefetchable memory
space. The amount of data that is pre-fetched depends on the type of transaction. The
amount of pre-fetching may also be affected by the amount of free buffer space available
in PI7C7300D, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFOs, and so on. The target device’s
base address register or registers indicate if a memory address region is prefetchable.
4.7.2
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C7300D requests one
and only one DWORD from the target and disconnects the initiator after delivery of the
first DWORD of read data. Unlike prefetchable read transactions, PI7C7300D forwards
the read byte enable information for the data phase.
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