參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 44/107頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標準包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 41 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
(offset 64h). PI7C7300D will report system error. See Section 7.4 for a description of
system error conditions.
4.9.4
TARGET TERMINATION INITIATED BY PI7C7300D
PI7C7300D can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
4.9.4.1
TARGET RETRY
PI7C7300D returns a target retry to the initiator when it cannot accept write data or
return read data as a result of internal conditions. PI7C7300D returns a target retry to an
initiator when any of the following conditions is met:
For delayed write transactions:
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
Target response has been received but has not progressed to the head of the return
queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C7300D, and the write transaction
is not a locked transaction.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
For delayed read transactions:
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a
posted write transaction precedes it.
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been
queued.
A locked sequence is being propagated across PI7C7300D, and the read transaction
is not a locked transaction.
PI7C7300D is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
For posted write transactions:
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C7300D, and the write transaction
is not a locked transaction.
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