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參數(shù)資料
| 型號： | PI7C7300DNAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 54/107頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 標準包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 50 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
PI7C7300D does not combine separate write transactions into a single write
transaction—this optimization is best implemented in the originating master.
PI7C7300D does not merge bytes on separate masked write transactions to the same
DWORD address—this optimization is also best implemented in the originating
master.
PI7C7300D does not collapse sequential write transactions to the same address into
a single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
6.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when
those transactions cross PI7C7300D.
The following general ordering guidelines govern transactions crossing PI7C7300D:
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order
with respect to other transactions that have been terminated with target retry. If the
order of completion of delayed requests is important, the initiator should not start a
second delayed transaction until the first one has been completed. If more than one
delayed transaction is initiated, the initiator should repeat all delayed transaction
requests, using some fairness algorithm. Repeating a delayed transaction cannot be
contingent on completion of another delayed transaction. Otherwise, a deadlock can
occur.
Write transactions flowing in one direction have no ordering requirements with
respect to write transactions flowing in the other direction. PI7C7300D can accept
posted write transactions on both interfaces at the same time, as well as initiate
posted write transactions on both interfaces at the same time.
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master.
This is true for PI7C7300D and must also be true for other bus agents. Otherwise, a
deadlock can occur.
PI7C7300D accepts posted write transactions, regardless of the state of completion
of any delayed transactions being forwarded across PI7C7300D.
6.3
ORDERING RULES
Table 6-1 shows the ordering relationships of all the transactions and refers by number to
the ordering rules that follow.
Table 6-1 SUMMARY OF TRANSACTION ORDERING
Pass
Posted
Write
Delayed
Read
Request
Delayed
Write
Request
Delayed Read
Completion
Delayed Write
Completion
Posted Write
No
1
Yes
5
Yes
5
Yes
5
Yes
5
Delayed Read Request
No
2
No
Yes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8140AMAE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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