參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 41/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標準包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 39 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
PI7C7300D handles these terminations in different ways, depending on the type of
transaction being performed.
4.9.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C7300D initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 4-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C7300D repeats a delayed write transaction until one of the following conditions is
met:
PI7C7300D completes at least one data transfer.
PI7C7300D receives a master abort.
PI7C7300D receives a target abort.
PI7C7300D makes 2
24 (default) or 232 (maximum) write attempts resulting in a response
of target retry.
Table 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination
Response
Normal
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Target Retry
Returning target retry to initiator. Continue write attempts to target
Target Disconnect
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Target Abort
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
After the PI7C7300D makes 2
24 (default) attempts of the same delayed write trans-action
on the target bus, PI7C7300D asserts P_SERR# if the SERR# enable bit (bit 8 of
command register for secondary bus S1 or S2) is set and the delayed-write-non- delivery
bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable
register (offset 64h). PI7C7300D will report system error. See Section 7.4 for a
description of system error conditions.
4.9.3.2
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C7300D initiates a posted write transaction, the target termination cannot be
passed back to the initiator. Table 4-8 shows the response to each type of target
termination that occurs during a posted write transaction.
Table 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
Target Termination
Repsonse
Normal
No additional action.
Target Retry
Repeating write transaction to target.
Target Disconnect
Initiate write transaction for delivering remaining posted write data.
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