參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 104/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 96 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
DWC (Row 5)
Yes
No
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must
complete on the target bus in the order in which they were received in the initiator bus.
In Row 2 Column1,DRR cannot pass the previous PMW and that means the previous
PMW heading to the same direction must be completed before the DRR can be attempted
on the target bus.
In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the
head of the delayed transaction queue.
15.3
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
15.3.1
MASTER ABORT
Master abort indicates that when PI7C7300D acts as a master and receives no response
(i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the
bridge deasserts FRAME# and then deasserts IRDY#.
15.3.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
S1_PAR, and S2_PAR signals. Parity should be even (i. e. an even number of‘1’s) across
AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are
valid. For reads, even parity must be generated using the initiators CBE signals combined
with the read data. Again, the PAR signal corresponds to read data from the previous
data phase cycle.
15.3.3
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after
the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register
are both set to 1. For write data phases, a parity error should be reported by asserting the
P_PERR# signal two cycles after the data phase and should remain asserted for one cycle
when bit 6 in the Command register is set to a 1. The target reports any type of data
parity errors during write cycles, while the master reports data parity errors during read
cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim
the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master
Abort. When the bridge is acting as master, a data parity error during a read cycle results
in the bridge master initiating a Master Abort.
相關(guān)PDF資料
PDF描述
PI7C8140AMAE IC PCI-PCI BRIDGE 2PORT 128-QFP
PI7C8150ANDE IC PCI-PCI BRIDGE 2PORT 256-PBGA
PI7C8150BNDIE IC PCI-PCI BRIDGE ASYNC 256-PBGA
PI7C8152BMAIE IC PCI-PCI BRIDGE 2PORT 160-MQFP
PI7C8154ANAE IC PCI-PCI BRIDGE ASYNC 304-PBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140AMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge
PI7C8140AMAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*