參數(shù)資料
型號： PI7C7300DNAE
廠商： Pericom
文件頁數(shù)： 60/107頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標準包裝： 40
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應商設備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 56 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
PI7C7300D sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on
the initiator bus and PI7C7300D has write status to return, the following events occur:
PI7C7300D first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two
cycles later, if the secondary interface parity-error-response bit is set in the bridge
control register (offset 3Ch).
PI7C7300D sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
PI7C7300D asserts P_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity-error-response bit is set in the command register of the primary
interface.
-
The parity-error-response bit is set in the bridge control register of the
secondary interface.
PI7C7300D completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the
following events occur:
PI7C7300D asserts S_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity error response bit is set in the command register of the primary
interface.
-
The parity error response bit is set in the bridge control register of the secondary
interface.
PI7C7300D completes the transaction normally.
7.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C7300D responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
PI7C7300D asserts P_PERR# two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C7300D sets the parity error detected bit in the status register of the primary
interface.
PI7C7300D captures and forwards the bad parity condition to the secondary bus.
PI7C7300D completes the transaction normally.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140AMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge
PI7C8140AMAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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