參數(shù)資料
型號(hào)： PI7C7300DNAE
廠商： Pericom
文件頁(yè)數(shù)： 38/107頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300D
3-PORT PCI-TO-PCI BRIDGE
Page 36 of 107
Pericom Semiconductor
November 2005 - Revision 1.01
PI7C7300D also supports Type 1 to Type 1 forwarding of configuration write
transactions upstream to support upstream special cycle generation. A Type 1
configuration command is forwarded upstream when the following conditions are met:
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive)
in the secondary bus number register and the upper limit (inclusive) in the
subordinate bus number register.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
The PI7C7300D forwards Type 1 to Type 1 configuration write transactions as delayed
transactions. Type 1 to Type 1 configuration write transactions are limited to a single
data transfer.
4.8.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in
hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and
are not forwarded across the bridge. Special cycle transactions can be generated from
Type 1 configuration write transactions in either the upstream or the down-stream
direction.
PI7C7300D initiates a special cycle on the target bus when a Type 1 configuration write
transaction is being detected on the initiating bus and the following conditions are met
during the address phase:
The lowest two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in
configuration space for downstream forwarding or equal to the value in the primary
bus number register in configuration space for upstream forwarding.
The bus command on CBE# is a configuration write command.
When PI7C7300D initiates the transaction on the target interface, the bus command is
changed from configuration write to special cycle. The address and data are for-warded
unchanged. Devices that use special cycles ignore the address and decode only the bus
command. The data phase contains the special cycle message. The transaction is
forwarded as a delayed transaction, but in this case the target response is not forwarded
back (because special cycles result in a master abort). Once the transaction is completed
on the target bus, through detection of the master abort condition, PI7C7300D responds
with TRDY# to the next attempt of the con-figuration transaction from the initiator. If
more than one data transfer is requested, PI7C7300D responds with a target disconnect
operation during the first data phase.
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