參數(shù)資料
型號: IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 99/131頁
文件大?。?/td> 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
I/O Definitions and Timing
Page 99 of 131
nDI2
Input,
active low
Serves as the driver inhibit for all chip test outputs. When a low level (`0'b) is applied
to this input, all chip test outputs are disabled. When this signal is inactive (`1'b), all
test outputs are controlled by the functional enable. This input enables exclusive con-
trol of the test outputs independently of their respective functional enable, for the pur-
pose of LSSD test.
SIDD
Input
Receiver inhibit and leakage current test.
WTEST
Input
Receiver inhibit for wafer test.
PLL_TESTIN
Input
Used during a test as the internal PLL test input.
PLL_TESTOUT
Output
Used during a test as the internal PLL test output
PLL_LOCK
Output
Set to ‘1’b when the PLL has attained phase lock.
DELAY_OUT
Output
Output of the internal delay element used for process measurement. The input to the
delay element is RAM_BURN_IN.
RAM_BURN_IN
Input
Performs a “burn-in” of the internal RAMs. Once the ABIST is started from the OCM,
the ABIST sequence will repeat itself until the device is reset.
Other Signals
PLL_VDDA
Input
3.3V PLL supply.
VREF_MS_IN
Input
1.5V voltage reference for MS_IN_ADDR HSTL receivers.
VREF_MS_OUT
Input
1.5V voltage reference for MS_OUT_ADDR HSTL receivers.
VREF_MS_SYNC
Input
1.5V voltage reference for MS_SYNC and MS_DASLSYNC HSTL receivers.
Table 21: Signal Definitions
(Page 6 of 6)
Signal Name
Type
Description
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