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| 型號： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 45/131頁 |
| 文件大小： | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Functional Description
Page 45 of 131
3.14.3 Packet Reception Window for Speed Expansion
Packets belonging to a group of related speed-expanded inputs must arrive within a specific window. The
reference point, the input that defines the packet arrival time Ta, is the master in a speed expanded configu-
ration. All other related inputs must receive packets between Ta - 1 byte clock and Ta + 1 byte clock.
3.14.4 Synchronization of Slave Device with Master Device
The master device and the slave device in an external speed expansion configuration must be synchronized.
This is done with SEQ_CLK sync pin, which can operate in one of the following modes:
When the PRS28.4G is configured as a master device in external speed expansion, or in single device
operation, the SEQ_CLK pin is programmed as an output. The device generates an internal sync signal
that is used for its internal timing. This internal sync signal appears on the SEQ_CLK output.
Note:
It is possible to configure the SEQ_CLK of the master as an input and to externally generate this
signal. However, this signal must be distributed to the master and the slave synchronously to the device
internal byte clocks.
When the PRS28.4G is configured as a slave device in external speed expansion, the SEQ_CLK must be
programmed as input. The sync signal that is used for the internal timing is taken from the SEQ_CLK
sync clock from the master.
Each PRS28.4G contains a sequencer. The SEQ_CLK sync signal is used to synchronize the sequencer in
the slave device with the sequencer in the master device. Both the master and slave sequencer are fully
synchronized. Therefore the SEQ_CLK is fully synchronous to the device internal logic.
3.14.5 Master Slave Address Communication
Two busses, one for the input section and one for the output section, are used to transfer addresses from the
master to the slave:
Each bus is synchronous with the internal byte clock.
When external speed expansion is disabled, the busses are tri-state.
When external speed expansion is enabled, and the device is programmed as a master, the busses are
configured as output.
When external speed expansion is enabled, and the device is programmed as a slave, the busses are
configured as input.
Table 12: Port Combination in Internal Port Expansion
Internal Speed
Expansion Mode
(configuration 0 register)
Configuration
Port Speed
Port Combination
0
16 x 16
1.77 Gb/s
none
1
8 x 8
3.54 Gb/s
0 and 8,
1 and 9,
...
7 and 15
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