參數(shù)資料
型號： IBM32NPR101EPXCAC133
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 94/131頁
文件大?。?/td> 1679K
代理商： IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
I/O Definitions and Timing
Page 94 of 131
prs28.03.fm
August 31, 2000
7. I/O Definitions and Timing
Table 21: Signal Definitions
(Page 1 of 6)
Signal Name
Type
Description
Clock and Reset Signals
SYS_CLK_Q
SYS_CLK_QN
Input,
differential
System clock used for the internal clock generation network. When the internal PLL is
enabled, SYS_CLK is equal to the internal byte clock divided by either two or four,
depending on the setting of the PLL register.
See
Electrical Characteristics
on page 125 for requirements on SYS_CLK.
When using an external PLL, SYS_CLK is a equal to the internal byte clock times 2,
with 50% duty cycle.
C_CLK_OUTQ
C_CLK_OUTQN
Output
differential
Free running C clock phase of the byte clock at the output of the internal clock tree.
When the internal PLL is used, this clock output will be at the correct frequency of
100
μ
s after the Clock Start OCM Event is sent. During Flush Reset and BIST, this sig-
nal is the free-running byte clock feeding the clock generation logic. During normal
operation, this signal is generated by the end of the C clock tree.
When using an external PLL, C_CLK_OUT is to be used as the PLL feedback clock.
nRESET
Input
active low
Must be active for at least four EMB clock cycles. Asserting this pin causes a reset of
all internal logic, except the IEEE 1149.1 (JTAG logic block). See
Reset, Initialization,
and Operation
on page 88 for details on the reset sequence.
SEQ_CLK
Bidirec-
tional
Low frequency clock used to synchronize the internal sequencers of different mod-
ules. For external speed expansion, it is a synchronous signal generated by the Mas-
ter device and fed to the slave device.
The period of this clock is equal to one-quarter of the total packet length in SYS_CLK
cycle units. Therefore, it can vary from 16 to 20 SYS_CLK cycles according to the
packet length.
The mode of operation of this pin is programmable via the Sequencer Sync Mode bit
in Configuration Register 0. It can be either tri-stated for single device operation, gen-
erated by the device, or received by the device.
This signal is HSTL level and can only be connected point to point.
SEQ_CLK_TTL
Output
Identical to the SEQ_CLK output, but is in TTL level, and is only used as an output
signal.
Data Signals
DATA_IN_[00:15]_Q(0:3)
DATA_IN_[00:15]_QN(0:3)
Input
DATA_IN_
n
_Q(
i
) and DATA_IN_
n
_QN(
i
) form one of the four 444 Mb/s differential
signals for input port
n
.
For each port, bits 0 and 1 carry the slave byte stream and bits 2 and 3 carry the mas-
ter byte stream (see
Physical Bit Organization of a Port
on page 27).
DATA_OUT_[00:15]_Q(0:3)
DATA_OUT_[00:15]_QN(0:3)
Output
DATA_OUT_
n
_Q(
i
) and DATA_OUT_
n
_QN(
i
) form one of the four 444 Mb/s differen-
tial signals for output port
n
.
For each port, bits 0 and 1 carry the slave byte stream and bits 2 and 3 carry the mas-
ter byte stream (see
Physical Bit Organization of a Port
on page 27).
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