參數(shù)資料
型號: IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 7/131頁
文件大?。?/td> 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet RoutingSwitch
prs28.03LOF.fm
August 31, 2000
List of Figures
Page 7 of 131
List of Figures
Figure 1: Pinout ........................................................................................................................................... 13
Figure 2: Block Diagram .............................................................................................................................. 14
Figure 3: Speed Expansion Block Diagram ................................................................................................. 22
Figure 4: Single Stage Port Expansion Block Diagram ............................................................................... 24
Figure 5: Packet Format 1.77 Gb/s Port ...................................................................................................... 25
Figure 6: Packet Format for 3.54 Gb/s Port ................................................................................................ 25
Figure 7: Idle Packet Format ....................................................................................................................... 28
Figure 8: Input-side Grant Operation ........................................................................................................... 38
Figure 9: OCM Interface Signals Timing Diagram ..................................................................................... 105
Figure 10: OCM Signal Timing Diagram .................................................................................................... 106
Figure 11: SND_GRANT(n) ....................................................................................................................... 107
Figure 12: RCV_GRANT(n) ....................................................................................................................... 107
Figure 13: Q_FULL, Q_EMPTY, Q_SYNC Timing Diagram ..................................................................... 108
Figure 14: Package Physical Dimensions ................................................................................................. 109
Figure 15: HSTL Termination .................................................................................................................... 128
Figure 16: DASL Termination for Slave LUs ............................................................................................. 128
Figure 17: DASL Termination for Master LUs, Bits 2 and 3 ...................................................................... 129
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